The conventional device is constituted such that, as shown in FIG. 1, a polysilicon layer 11 is let to form a node, and is bury-contacted to an N+ drain 4b, and upon the polysilicon layer 11, there is formed a dielectric layer 12 (nitride layer/oxide layer) by applying a thermal growing process, while a polysilicon plate 13 is formed upon the dielectric layer 12, thereby forming a single type capacitor.
That is, as shown in FIG. 1, according to the conventional device, the area of the dielectric layer 12 constitutes the area of the capacitor area, an the single type capacitor consists of the polysilicon layer 11 (node polysilicon layer) and the polysilicon 13 (plate polysilicon layer).
In FIG. 1, element code 3 indicates an LT01 oxide layer which forms the side wall of the gate, element code 15 indicates stacked polysilicon layers which are stacked in order to increase the length of the capacitor in the vertical direction, element code 16 indicates an LT02 layer (Low Temperature Oxide layer) which is formed on the polysilicon layer 13, and element code 17 indicates a BPSG layer (Boro-Phosphor-Silicate glass layer) which is formed on the LT02 layer 16.
The conventional technique described above has disadvantages such that the reliability of the device is lowered due to the etch damages which are liable to occur during the etching of the trench of the polysilicon layer 15, that step coverage problems occur during the formation of the multiple thin layers because of the large vertical/horizontal aspect ratio, and that a difficulty is encountered in increasing the capacitance of the high density device under a limited space.
As more advanced techniques, there have been developed a T type double stacked capacitor by Hitachi company and a fin type stacked capacitor by Fujitsu company. However, these techniques are complicated and highly fastedious, and also include many different processes in practice.